The present invention relates to passivation of surface states created during fabrication or operation of integrated circuit structures such as a field effect transistor (FET).
It is known in the art that conventional integrated circuit fabrication techniques may create defective film interfaces that are manifested electronically as surface states. For instance, such defective film interfaces may arise in a film growth step, or may be created by charging damage, such as from high energy plasma processes used to pattern contact vias or conductive lines. Surface states may also arise from voltage stress during operation. Weak or open bonds that result from damage to the chemical bonds at an interface, called xe2x80x9cdangling bonds,xe2x80x9d are one type of defective film interface that may cause a surface state.
Referring now to FIG. 1, there is shown a typical metal-oxide-semiconductor (MOS) gate conductor 90 of the prior art located on a substrate 100. Substrate 100 typically comprises doped silicon and includes implanted source and drain regions 120. Over implanted source and drain regions 120 is deposited a gate dielectric layer 110, commonly an oxide or an oxide-nitride composite. Gate conductor 90 comprises a polysilicon layer 130, a silicide layer 140, and an insulator layer 150, each layer deposited and patterned by conventional lithographic and etching techniques well known in the art. A typical gate conductor 90 may or may not contain the silicide layer 140. Insulator layer 150 electrically insulates the gate conductor 90 and is most commonly oxide or nitride. Insulator layer 150 may also serve as the etch mask. A spacer film 160 can be used to create a lightly doped junction near the gate. The spacer film 160 may or may not contain a layer created by thermally oxidizing the polysilicon layer 130.
An encapsulating film 170, typically comprising silicon nitride, may be deposited over the entire gate conductor and substrate structure. Encapsulation protects the devices from mobile ion contamination from such elements as sodium or potassium. Unfortunately, encapsulation also prevents passivating species such as hydrogen or fluorine from diffusing from overlying films directly to critical interfaces (described below), except through openings such as for device contacts.
Dangling bonds 105 are typically formed during processing, as described above, at the interface between gate dielectric 110 and silicon substrate 100. Dangling bonds 105 are indicated by dashes in FIG. 1. Because the edge or corner of the gate conductor 90 has the highest potential on the gate dielectric, the edge region 95 is most susceptible to damage and surface state formation.
At critical device interfaces, such as the interface between gate dielectric 110 and silicon substrate 100, dangling bonds 105 promote electron-hole pair recombination. Excessive electron-hole recombination is measured as high device leakage. Such leakage can adversely impact device performance through threshold voltage, data retention time, and standby power degradation.
Dangling bonds 105 can be repaired or passivated by reacting with a suitable reactant. The most widely used method to passivate surface states is by annealing the devices in hydrogen or forming gas at approximately 400-450xc2x0 C. This anneal is thought to allow hydrogen to diffuse to the interface between gate dielectric 110 and silicon substrate 100 where hydrogen atoms terminate the dangling bonds. Injected hot electrons can easily break hydrogen or hydroxyl terminated bonds, however, thereby de-passivating and regenerating the surface states. Thus, hydrogen passivation increases susceptibility to hot electron degradation over time, reducing reliability.
It is also known that fluorine may be used to repair or passivate dangling bonds 105. Fluorine binds to silicon dangling bonds more strongly than hydrogen, forming a much more robust passivant and reducing gate-induced device leakage (GIDL). As a more effective passivant, fluorine is harder to remove than hydrogen during thermal or voltage stress, thus improving device reliability.
Direct addition of fluorine to the gate dielectric, either by implantation or by doping, may be insufficient, however, to heal damage such as charge-related damage caused by high energy plasma processes during later contact or wiring level fabrication. Excess fluorine at the gate also may degrade device performance by thickening the gate dielectric, which is particularly undesirable for thin gates (less than 100 Angstroms thick). Residual fluorine in the gate dielectric due to a BF2+ implant has also been reported to increase the hot electron resistance of devices. Similarly, excess implanted fluorine in gate polysilicon can diffuse out and produce a more hot-electron resistant interface. Thus, direct addition of fluorine to the gate dielectric or gate polysilicon layer has numerous drawbacks.
Reliable surface state passivation is still needed, however, for integrated circuits to survive packaging thermal cycles or device end-of-life conditions, as simulated by reliability stressing. Therefore, there is a need to provide the benefits of fluorine surface state passivation without causing undesired thickening of the gate dielectric.
To meet this and other needs, and in view of its purposes, the present invention provides a method for passivating surface states in an integrated circuit structure comprising a gate conductor having a gate dielectric layer. The method comprises, as its primary step, fabricating a solid state source of fluorine in close proximity to the gate dielectric layer. The present invention further encompasses an integrated circuit structure comprising a substrate having a gate dielectric layer on the substrate; a gate conductor on the substrate above the gate dielectric layer; and a solid state source of fluorine in close proximity to the gate dielectric layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.